1. Field of the Invention
This invention relates to integrated circuits and more particularly, to a method of forming an integrated circuit assembly.
2. Description of the Prior Art
In the manuafacture of electronic circuitry, the use of discrete electrical components, such as resistors, capacitors, and transistors, is rapidly becoming obsolete. These discrete components are largely being supplanted by the integrated circuit, a small chip typically comprising silicon which, by a series of selected masking, etching, and processing steps, can be made to perform all of the functions which may be performed by discrete components when these discrete components are suitably interconnected by conventional or printed wiring to form an operating circuit.
Integrated circuit devices are very small, the dimensions of a typical device being approximately 0.035 .times. 0.035 inch. These microscopic dimensions permit a heretofore undreamed of degree of miniaturization and significantly improve the operating characteristics of circuits which are fabricated on integrated circuit devices. For example, the switching speed of gating circuits and the bandwidth of I.F. amplifiers, are significantly improved by this miniaturization.
Of course, an integrated circuit cannot operate in vacuo, and must be interconnected with other integrated circuits and to other electrical components such as power supplies, input/output devices, and the like. Here, however, the microscopic dimensions are a distinct disadvantage.
Because of improved manufacturing techniques and increased yield, the cost of integrated circuits has dropped drastically in the last decade and now, in many instances, the cost of packaging or assembling such circuits so that they may be interconnected with other electrical components has become significant and approaches a most undesirable situation.
In one prior art method of packaging integrated circuit devices, each device is bonded to the header of a multiterminal base. Fine gold wires are then hand bonded, one at a time, from the terminal portions of the integrated circuit to corresponding terminal pins on the base, which pins, of course, extend up through the header for this purpose, in a well-known manner. Interconnection of the device with other devices is then made by plugging the base into a conventional socket which is wired to other similar sockets, or to discrete components, by conventional wiring or by printed circuitry.
In another prior art method of packaging integrated circuit devices, a lead frame is first formed by punching or stamping or etching a suitable metallic strip such as a copper strip. The lead frame may then be gold plated to facilitate bonding thereto. A semiconductor chip is then bonded by means of conductive wires to mounting areas provided on the lead frame. The bonded semiconductor chip may then be interconnected to another device by bonding conductive wires thereto. The thus bonded and interconnected chip is then encapsulated.
The use of a lead frame and wire bonding is limited especially as the number of leads to be bonded increases. With increasing connections, processing not only becomes more difficult, but also more expensive. A technique for forming an assembly comprising an integrated circuit chip with beam leads conductively connected to an external lead or terminal without wire bonding is desired.
U.S. Pat. No. 3,325,379 reveals an electroplating method of making metallic patterns having continuous interconnections. However, a method of forming an integrated circuit package which avoids a separate wire bonding step and in which interconnected terminals are formed along with a self-supporting assembly has not heretofore been described.